Difference between revisions of "SHA-3 Hardware Implementations"

From The ECRYPT Hash Function Website
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This page tries to summarize the key properties of reported hardware implementations of the SHA-3 candidates. The implementations are categorized into FPGA and standard-cell ASIC implementations. The reported results are usually the output of various hardware synthesis tools.
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== High-Speed Implementations (FPGA) ==
 
== High-Speed Implementations (FPGA) ==
  
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(*) Estimation for 64-bit memory interface based on published performance figures.
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(*) Estimation for 64-bit memory interface based on published performance figures: (1024 bits/permutation) * (100 * 10^6 cycles/s) / (3870 cycles/permutation) = 26.46 * 10^6 bits/s

Revision as of 10:42, 7 November 2008

This page tries to summarize the key properties of reported hardware implementations of the SHA-3 candidates. The implementations are categorized into FPGA and standard-cell ASIC implementations. The reported results are usually the output of various hardware synthesis tools.


1 High-Speed Implementations (FPGA)

Note: The size and fuctionality of slices varies between FPGA families. The slice count of implementations on different FPGA families should therefore not be used to make a direct comparison.

Hash Function Name Reference Implementation Details Technology Size Throughput Clock Frequency
Grøstl-224/256 Submission document P & Q permutation in parallel Xilinx Spartan 3 6582 slices 4439 Mbit/s 86.7 MHz
Grøstl-224/256 Submission document P & Q permutation in parallel Xilinx Virtex 5 1722 slices 10276 Mbit/s 200.7 MHz
Grøstl-384/512 Submission document P & Q permutation in parallel Xilinx Spartan 3 20233 slices 5901 Mbit/s 80.7 MHz
Grøstl-384/512 Submission document P & Q permutation in parallel Xilinx Virtex 5 5419 slices 15395 Mbit/s 210.5 MHz
MD6 Submission document Compression function only, 16 parallel steps Xilinx Virtex-II Pro 5313 slices 1232 Mbit/s 150.3 MHz
MD6 Submission document Compression function only, 32 parallel steps Xilinx Virtex-II Pro 7529 slices 1894 Mbit/s 141.6 MHz



2 High-Speed Implementations (ASIC)

Hash Function Name Reference Implementation Details Technology Size Throughput Clock Frequency
Grøstl-224/256 Submission document P & Q permutation in parallel UMC 0.18 µm 131 kGates 4379 Mbit/s 85.5 MHz
Grøstl-384/512 Submission document P & Q permutation in parallel UMC 0.18 µm 341 kGates 6225 Mbit/s 85.1 MHz
Keccak Submission document Core (round function, state register) & IO buffer ST 0.13 µm 48 kGates 28400 Mbit/s 500 MHz
Keccak Submission document Core (round function, state register) only ST 0.13 µm 40 kGates 15000 Mbit/s 500 MHz
MD6 Submission document Compression function only, 48 parallel steps GPDSK 90 nm 145 kGates N/A 200 MHz
MD6 Submission document Compression function & memory control logic, 16 parallel steps GPDSK 90 nm 105 kGates N/A 200 MHz



3 Low-Area Implementations (ASIC)

Hash Function Name Reference Implementation Details Technology Size Throughput Clock Frequency
Keccak Submission document Core using system memory ST 0.13 µm 6 kGates 26 Mbit/s(*) 100 MHz

(*) Estimation for 64-bit memory interface based on published performance figures: (1024 bits/permutation) * (100 * 10^6 cycles/s) / (3870 cycles/permutation) = 26.46 * 10^6 bits/s