Difference between revisions of "SHA-3 Hardware Implementations"

From The ECRYPT Hash Function Website
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{| border="1" cellpadding="4" cellspacing="0" align="center" class="wikitable"
 
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! width="120"| Hash Function Name  !! width="150"| Reference  !! width="200"| Implementation Details  !! width="150"| Technology  !! width="100"| Size  !! width="100"| Throughput  !!  width="100"| Clock Frequency
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! width="120"| Hash Function Name  !! width="150"| Reference  !! width="200"| Implementation Details  !! width="100"| Technology  !! width="80"| Size  !! width="80"| Throughput  !!  width="80"| Clock Frequency
 
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| Grøstl-224/256  || Submission document  || P & Q permutation in parallel  || Xilinx Spartan 3  || 6582 slices  || 4439 Mbit/s  || 86.7 MHz
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| Grøstl-224/256  || Submission document  || P & Q permutation in parallel  || Xilinx Spartan 3  || align="right"| 6582 slices  || align="right"| 4439 Mbit/s  || align="right"| 86.7 MHz
 
|-
 
|-
| Grøstl-224/256  || Submission document  || P & Q permutation in parallel  || Xilinx Virtex 5  || 1722 slices  || 10276 Mbit/s  || 200.7 MHz
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| Grøstl-224/256  || Submission document  || P & Q permutation in parallel  || Xilinx Virtex 5  || align="right"| 1722 slices  || align="right"| 10276 Mbit/s  || align="right"| 200.7 MHz
 
|-
 
|-
| Grøstl-384/512  || Submission document  || P & Q permutation in parallel  || Xilinx Spartan 3  || 20233 slices  || 5901 Mbit/s  || 80.7 MHz
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| Grøstl-384/512  || Submission document  || P & Q permutation in parallel  || Xilinx Spartan 3  || align="right"| 20233 slices  || align="right"| 5901 Mbit/s  || align="right"| 80.7 MHz
 
|-
 
|-
| Grøstl-384/512  || Submission document  || P & Q permutation in parallel  || Xilinx Virtex 5  || 5419 slices  || 15395 Mbit/s  || 210.5 MHz
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| Grøstl-384/512  || Submission document  || P & Q permutation in parallel  || Xilinx Virtex 5  || align="right"| 5419 slices  || align="right"| 15395 Mbit/s  || align="right"| 210.5 MHz
 
|-
 
|-
| MD6  || Submission document|| Compression function only, 16 parallel steps || Xilinx Virtex-II Pro || 5313 slices  || 1232 Mbit/s  || 150.3 MHz
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| MD6  || Submission document|| Compression function only, 16 parallel steps || Xilinx Virtex-II Pro || align="right"| 5313 slices  || align="right"| 1232 Mbit/s  || align="right"| 150.3 MHz
 
|-
 
|-
| MD6  || Submission document|| Compression function only, 32 parallel steps || Xilinx Virtex-II Pro || 7529 slices  || 1894 Mbit/s  || 141.6 MHz
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| MD6  || Submission document|| Compression function only, 32 parallel steps || Xilinx Virtex-II Pro || align="right"| 7529 slices  || align="right"| 1894 Mbit/s  || align="right"| 141.6 MHz
 
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{| border="1" cellpadding="4" cellspacing="0" align="center" class="wikitable"
 
{| border="1" cellpadding="4" cellspacing="0" align="center" class="wikitable"
 
|- style="background:#efefef;"
 
|- style="background:#efefef;"
! width="120"| Hash Function Name  !! width="150"| Reference  !! width="200"| Implementation Details  !! width="150"| Technology  !! width="100"| Size  !! width="100"| Throughput  !!  width="100"| Clock Frequency
+
! width="120"| Hash Function Name  !! width="150"| Reference  !! width="200"| Implementation Details  !! width="100"| Technology  !! width="80"| Size  !! width="80"| Throughput  !!  width="80"| Clock Frequency
 
|-
 
|-
| Grøstl-224/256  || Submission document  || P & Q permutation in parallel  || UMC 0.18 µm  || 131 kGates  || 4379 Mbit/s  || 85.5 MHz
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| Grøstl-224/256  || Submission document  || P & Q permutation in parallel  || UMC 0.18 µm  || align="right"| 131 kGates  || align="right"| 4379 Mbit/s  || align="right"| 85.5 MHz
 
|-
 
|-
| Grøstl-384/512  || Submission document  || P & Q permutation in parallel  || UMC 0.18 µm  || 341 kGates  || 6225 Mbit/s  || 85.1 MHz
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| Grøstl-384/512  || Submission document  || P & Q permutation in parallel  || UMC 0.18 µm  || align="right"| 341 kGates  || align="right"| 6225 Mbit/s  || align="right"| 85.1 MHz
 
|-
 
|-
| Keccak  || Submission document  || Core (round function, state register) & IO buffer  || ST 0.13 µm  || 48 kGates  || 28400 Mbit/s  || 500 MHz
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| Keccak  || Submission document  || Core (round function, state register) & IO buffer  || ST 0.13 µm  || align="right"| 48 kGates  || align="right"| 28400 Mbit/s  || align="right"| 500 MHz
 
|-
 
|-
| Keccak  || Submission document  || Core (round function, state register) only || ST 0.13 µm  || 40 kGates  || 15000 Mbit/s  || 500 MHz
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| Keccak  || Submission document  || Core (round function, state register) only || ST 0.13 µm  || align="right"| 40 kGates  || align="right"| 15000 Mbit/s  || align="right"| 500 MHz
 
|-
 
|-
| MD6  || Submission document  || Compression function only, 48 parallel steps  || GPDSK 90 nm  || 145 kGates  || N/A  || 200 MHz
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| MD6  || Submission document  || Compression function only, 48 parallel steps  || GPDSK 90 nm  || align="right"| 145 kGates  || align="right"| N/A  || align="right"| 200 MHz
 
|-
 
|-
| MD6  || Submission document  || Compression function & memory control logic, 16 parallel steps || GPDSK 90 nm || 105 kGates  || N/A  || 200 MHz
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| MD6  || Submission document  || Compression function & memory control logic, 16 parallel steps || GPDSK 90 nm || align="right"| 105 kGates  || align="right"| N/A  || align="right"| 200 MHz
 
|}
 
|}
  
  
 
== Low-Area Implementations (ASIC) ==
 
== Low-Area Implementations (ASIC) ==
 
 
{| border="1" cellpadding="4" cellspacing="0" align="center" class="wikitable"
 
{| border="1" cellpadding="4" cellspacing="0" align="center" class="wikitable"
 
|- style="background:#efefef;"
 
|- style="background:#efefef;"
! width="120"| Hash Function Name  !! width="150"| Reference  !! width="200"| Implementation Details  !! width="150"| Technology  !! width="100"| Size  !! width="100"| Throughput  !!  width="100"| Clock Frequency
+
! width="120"| Hash Function Name  !! width="150"| Reference  !! width="200"| Implementation Details  !! width="100"| Technology  !! width="80"| Size  !! width="80"| Throughput  !!  width="80"| Clock Frequency
 
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|-
| Keccak  || Submission document  || Core using system memory || ST 0.13 µm  || 6 kGates  || 26 Mbit/s*  || 100 MHz
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| Keccak  || Submission document  || Core using system memory || ST 0.13 µm  || align="right"| 6 kGates  || align="right"| 26 Mbit/s(*) || align="right"| 100 MHz
 
|}
 
|}
  
* Estimation for 64-bit memory interface based on published performance figures.
+
(*) Estimation for 64-bit memory interface based on published performance figures.

Revision as of 17:06, 6 November 2008

1 High-Speed Implementations (FPGA)

Hash Function Name Reference Implementation Details Technology Size Throughput Clock Frequency
Grøstl-224/256 Submission document P & Q permutation in parallel Xilinx Spartan 3 6582 slices 4439 Mbit/s 86.7 MHz
Grøstl-224/256 Submission document P & Q permutation in parallel Xilinx Virtex 5 1722 slices 10276 Mbit/s 200.7 MHz
Grøstl-384/512 Submission document P & Q permutation in parallel Xilinx Spartan 3 20233 slices 5901 Mbit/s 80.7 MHz
Grøstl-384/512 Submission document P & Q permutation in parallel Xilinx Virtex 5 5419 slices 15395 Mbit/s 210.5 MHz
MD6 Submission document Compression function only, 16 parallel steps Xilinx Virtex-II Pro 5313 slices 1232 Mbit/s 150.3 MHz
MD6 Submission document Compression function only, 32 parallel steps Xilinx Virtex-II Pro 7529 slices 1894 Mbit/s 141.6 MHz


2 High-Speed Implementations (ASIC)

Hash Function Name Reference Implementation Details Technology Size Throughput Clock Frequency
Grøstl-224/256 Submission document P & Q permutation in parallel UMC 0.18 µm 131 kGates 4379 Mbit/s 85.5 MHz
Grøstl-384/512 Submission document P & Q permutation in parallel UMC 0.18 µm 341 kGates 6225 Mbit/s 85.1 MHz
Keccak Submission document Core (round function, state register) & IO buffer ST 0.13 µm 48 kGates 28400 Mbit/s 500 MHz
Keccak Submission document Core (round function, state register) only ST 0.13 µm 40 kGates 15000 Mbit/s 500 MHz
MD6 Submission document Compression function only, 48 parallel steps GPDSK 90 nm 145 kGates N/A 200 MHz
MD6 Submission document Compression function & memory control logic, 16 parallel steps GPDSK 90 nm 105 kGates N/A 200 MHz


3 Low-Area Implementations (ASIC)

Hash Function Name Reference Implementation Details Technology Size Throughput Clock Frequency
Keccak Submission document Core using system memory ST 0.13 µm 6 kGates 26 Mbit/s(*) 100 MHz

(*) Estimation for 64-bit memory interface based on published performance figures.