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• 17:38, 22 May 2012 (diff | hist) . . (+1,300)‎ . . m SHA-3 Hardware Implementations Round Three ‎
• 16:50, 22 May 2012 (diff | hist) . . (+402)‎ . . m SHA-3 Hardware Implementations Round Three ‎
• 14:30, 22 May 2012 (diff | hist) . . (+32)‎ . . m SHA-3 Hardware Implementations Round Three ‎
• 14:26, 22 May 2012 (diff | hist) . . (+177,923)‎ . . Nm SHA-3 Hardware Implementations Round Three ‎ (Created a scratch page for building the round three page)
• 14:19, 22 May 2012 (diff | hist) . . (+177,798)‎ . . Nm SHA-3 Hardware Implementations Round Two ‎ (Created archived version of round two page) (current)
• 16:29, 20 January 2011 (diff | hist) . . (+49)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Updated results according to latest revision of the paper on Eprint)
• 15:57, 20 January 2011 (diff | hist) . . (-341)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Updated results from Homsirikamol et al. (from revised Eprint paper version))
• 14:13, 20 January 2011 (diff | hist) . . (+29)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Updated source code availability)
• 14:12, 20 January 2011 (diff | hist) . . (+1,623)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Updated source code availability for reference [30])
• 13:31, 22 November 2010 (diff | hist) . . (+588)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added link for HDL sources for Guo et al. [35])
• 13:24, 22 November 2010 (diff | hist) . . (+42)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added link to HDL source)
• 13:11, 9 November 2010 (diff | hist) . . (+383)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added Virtex 5 result from updated [27])
• 13:09, 9 November 2010 (diff | hist) . . (0)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Updated ref [27])
• 13:08, 9 November 2010 (diff | hist) . . (+19)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Updated ref [27])
• 11:30, 19 October 2010 (diff | hist) . . (+868)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added results from El Hadedy et al. ([41]))
• 11:21, 19 October 2010 (diff | hist) . . (+284)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for El Hadedy et al. ([41]))
• 12:41, 12 October 2010 (diff | hist) . . (-117)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Updated reference [30])
• 12:39, 12 October 2010 (diff | hist) . . (+4,306)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added Altera Stratix III results from Homsirikamol et al.)
• 12:19, 12 October 2010 (diff | hist) . . (+2,052)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Replaced Virtex 5 results from Gaj et al. (CHES 2010) with those of Homsirikamol et al.)
• 12:01, 12 October 2010 (diff | hist) . . (+12,394)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Updated results from Gaj et al. (CHES 2010) with results from Homsirikamol et al.)

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