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• 13:24, 22 November 2010 (diff | hist) . . (+42)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added link to HDL source)
• 13:11, 9 November 2010 (diff | hist) . . (+383)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added Virtex 5 result from updated [27])
• 13:09, 9 November 2010 (diff | hist) . . (0)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Updated ref [27])
• 13:08, 9 November 2010 (diff | hist) . . (+19)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Updated ref [27])
• 11:30, 19 October 2010 (diff | hist) . . (+868)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added results from El Hadedy et al. ([41]))
• 11:21, 19 October 2010 (diff | hist) . . (+284)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for El Hadedy et al. ([41]))
• 12:41, 12 October 2010 (diff | hist) . . (-117)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Updated reference [30])
• 12:39, 12 October 2010 (diff | hist) . . (+4,306)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added Altera Stratix III results from Homsirikamol et al.)
• 12:19, 12 October 2010 (diff | hist) . . (+2,052)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Replaced Virtex 5 results from Gaj et al. (CHES 2010) with those of Homsirikamol et al.)
• 12:01, 12 October 2010 (diff | hist) . . (+12,394)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Updated results from Gaj et al. (CHES 2010) with results from Homsirikamol et al.)
• 12:04, 15 September 2010 (diff | hist) . . (+368)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Added results from RCIS webpage [39])
• 12:03, 15 September 2010 (diff | hist) . . (+741)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from RCIS webpage [39])
• 11:56, 15 September 2010 (diff | hist) . . (+139)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for RCIS webpage (other ASIC implementations))
• 18:03, 14 September 2010 (diff | hist) . . (+93)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Satoh et al. [38])
• 18:00, 14 September 2010 (diff | hist) . . (+423)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Added results from Satoh et al. [38])
• 17:55, 14 September 2010 (diff | hist) . . (+372)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Satoh et al. [38])
• 17:49, 14 September 2010 (diff | hist) . . (+338)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Satoh et al.)
• 17:30, 14 September 2010 (diff | hist) . . (+5,223)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added ASIC results for implementations of Matsuo et al. (from [37]))
• 17:21, 14 September 2010 (diff | hist) . . (+113)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for standard-cell versions of implementations from Matsuo et al.)
• 17:18, 14 September 2010 (diff | hist) . . (+2,648)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added 90 nm results from RCIS webpage)
• 12:41, 14 September 2010 (diff | hist) . . (+1,092)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added link to HDL sources for [33])
• 12:31, 14 September 2010 (diff | hist) . . (+77)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added link to HDL sources for Matsuo et al.)
• 20:32, 6 September 2010 (diff | hist) . . (-4)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Corrected gate count for Guo et al. and Akin et al.)
• 20:28, 6 September 2010 (diff | hist) . . (-1)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Corrected gate count)
• 20:26, 6 September 2010 (diff | hist) . . (-5)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Blue Midnight Wish, Keccak, Luffa: Corrected gate count)
• 20:25, 6 September 2010 (diff | hist) . . (+360)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Walker et al.)
• 20:21, 6 September 2010 (diff | hist) . . (+259)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Walker et al.)
• 20:18, 6 September 2010 (diff | hist) . . (+4,509)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Guo et al.)
• 20:13, 6 September 2010 (diff | hist) . . (+2,490)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results from Guo et al.)
• 20:02, 6 September 2010 (diff | hist) . . (+37)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added note that results listed for Tillich et al. are just the post-synthesis ones.)
• 20:01, 6 September 2010 (diff | hist) . . (+341)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Guo et al.)
• 19:45, 6 September 2010 (diff | hist) . . (+1,094)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Akin et al.)
• 19:43, 6 September 2010 (diff | hist) . . (+3,365)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Akin et al.)
• 19:40, 6 September 2010 (diff | hist) . . (+1)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Blue Midnight Wish, Keccak, Luffa)
• 19:34, 6 September 2010 (diff | hist) . . (+5,017)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results from Akin et al.)
• 19:13, 6 September 2010 (diff | hist) . . (+403)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Akin et al.)
• 19:05, 6 September 2010 (diff | hist) . . (+4,889)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Matsuo et al.)
• 18:59, 6 September 2010 (diff | hist) . . (+2,476)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Addes results from Matsuo et al.)
• 18:42, 6 September 2010 (diff | hist) . . (+415)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Matsuo et al.)
• 18:36, 6 September 2010 (diff | hist) . . (+762)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added results from El Hadedy et al.)
• 18:28, 6 September 2010 (diff | hist) . . (+379)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for El Hadedy et al.)
• 18:23, 6 September 2010 (diff | hist) . . (+10,721)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Baldwin et al. (2nd SHA-3))
• 18:14, 6 September 2010 (diff | hist) . . (+4,099)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results from Baldwin et al. (no wrapper, long messages))
• 17:30, 6 September 2010 (diff | hist) . . (+351)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Baldwin et al. (2nd SHA-3 workshop))
• 17:07, 6 September 2010 (diff | hist) . . (+4,036)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Gaj et al. (Xilinx 5 ATHENa benchmarking))
• 16:43, 6 September 2010 (diff | hist) . . (+369)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Gaj et al.)
• 16:40, 6 September 2010 (diff | hist) . . (+2,631)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results from Gaj et al. (for Virtex 5))
• 16:15, 6 September 2010 (diff | hist) . . (+5,110)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Henzen et al.)
• 16:08, 6 September 2010 (diff | hist) . . (0)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates)
• 16:04, 6 September 2010 (diff | hist) . . (+563)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added implementation details for Henzen et al.)

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