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• 13:24, 22 November 2010 (diff | hist) . . (+42)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added link to HDL source)
• 13:11, 9 November 2010 (diff | hist) . . (+383)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added Virtex 5 result from updated [27])
• 13:09, 9 November 2010 (diff | hist) . . (0)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Updated ref [27])
• 13:08, 9 November 2010 (diff | hist) . . (+19)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Updated ref [27])
• 11:30, 19 October 2010 (diff | hist) . . (+868)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added results from El Hadedy et al. ([41]))
• 11:21, 19 October 2010 (diff | hist) . . (+284)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for El Hadedy et al. ([41]))
• 12:41, 12 October 2010 (diff | hist) . . (-117)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Updated reference [30])
• 12:39, 12 October 2010 (diff | hist) . . (+4,306)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added Altera Stratix III results from Homsirikamol et al.)
• 12:19, 12 October 2010 (diff | hist) . . (+2,052)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Replaced Virtex 5 results from Gaj et al. (CHES 2010) with those of Homsirikamol et al.)
• 12:01, 12 October 2010 (diff | hist) . . (+12,394)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Updated results from Gaj et al. (CHES 2010) with results from Homsirikamol et al.)
• 12:04, 15 September 2010 (diff | hist) . . (+368)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Added results from RCIS webpage [39])
• 12:03, 15 September 2010 (diff | hist) . . (+741)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from RCIS webpage [39])
• 11:56, 15 September 2010 (diff | hist) . . (+139)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for RCIS webpage (other ASIC implementations))
• 18:03, 14 September 2010 (diff | hist) . . (+93)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Satoh et al. [38])
• 18:00, 14 September 2010 (diff | hist) . . (+423)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (ASIC): Added results from Satoh et al. [38])
• 17:55, 14 September 2010 (diff | hist) . . (+372)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Satoh et al. [38])
• 17:49, 14 September 2010 (diff | hist) . . (+338)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Satoh et al.)
• 17:30, 14 September 2010 (diff | hist) . . (+5,223)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added ASIC results for implementations of Matsuo et al. (from [37]))
• 17:21, 14 September 2010 (diff | hist) . . (+113)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for standard-cell versions of implementations from Matsuo et al.)
• 17:18, 14 September 2010 (diff | hist) . . (+2,648)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added 90 nm results from RCIS webpage)

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