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• 19:13, 6 September 2010 (diff | hist) . . (+403)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Akin et al.)
• 19:05, 6 September 2010 (diff | hist) . . (+4,889)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Matsuo et al.)
• 18:59, 6 September 2010 (diff | hist) . . (+2,476)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Addes results from Matsuo et al.)
• 18:42, 6 September 2010 (diff | hist) . . (+415)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Matsuo et al.)
• 18:36, 6 September 2010 (diff | hist) . . (+762)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Low-Area Implementations (FPGA): Added results from El Hadedy et al.)
• 18:28, 6 September 2010 (diff | hist) . . (+379)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for El Hadedy et al.)
• 18:23, 6 September 2010 (diff | hist) . . (+10,721)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Baldwin et al. (2nd SHA-3))
• 18:14, 6 September 2010 (diff | hist) . . (+4,099)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results from Baldwin et al. (no wrapper, long messages))
• 17:30, 6 September 2010 (diff | hist) . . (+351)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Baldwin et al. (2nd SHA-3 workshop))
• 17:07, 6 September 2010 (diff | hist) . . (+4,036)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added results from Gaj et al. (Xilinx 5 ATHENa benchmarking))
• 16:43, 6 September 2010 (diff | hist) . . (+369)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Gaj et al.)
• 16:40, 6 September 2010 (diff | hist) . . (+2,631)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results from Gaj et al. (for Virtex 5))
• 16:15, 6 September 2010 (diff | hist) . . (+5,110)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (ASIC): Added results from Henzen et al.)
• 16:08, 6 September 2010 (diff | hist) . . (0)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates)
• 16:04, 6 September 2010 (diff | hist) . . (+563)‎ . . m SHA-3 Hardware Implementations ‎ (→‎All 14 Round-Two Candidates: Added implementation details for Henzen et al.)
• 15:55, 6 September 2010 (diff | hist) . . (+362)‎ . . m SHA-3 Hardware Implementations ‎ (→‎References: Added reference for Henzen et al.)
• 15:51, 6 September 2010 (diff | hist) . . (+2,484)‎ . . m SHA-3 Hardware Implementations ‎ (→‎Comparative Studies: Added results for 20 Gbps target from Henzen et al.)
• 15:12, 6 September 2010 (diff | hist) . . (+771)‎ . . m SHA-3 Hardware Implementations ‎ (Added section for ongoing HW benchmarking efforts (mentioning ATHENa))
• 15:48, 31 August 2010 (diff | hist) . . (+1,528)‎ . . m SHA-3 Hardware Implementations ‎ (→‎High-Speed Implementations (FPGA): Added tradeoff implementations from Ramakers and Narinx)
• 15:44, 31 August 2010 (diff | hist) . . (+470)‎ . . m SHA-3 Hardware Implementations ‎ (→‎ECHO, Hamsi, Luffa: Added tradeoff versions from Ramakers and Narinx)

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