SHA-3 Hardware Implementations

1 High-Speed Implementations (FPGA)

Hash Function Name	Reference	Implementation Details	Technology	Size	Throughput	Clock Frequency
Grøstl-224/256	Submission document	P & Q permutation in parallel	Xilinx Spartan 3	6582 slices	4439 Mbit/s	86.7 MHz
Grøstl-224/256	Submission document	P & Q permutation in parallel	Xilinx Virtex 5	1722 slices	10276 Mbit/s	200.7 MHz
Grøstl-384/512	Submission document	P & Q permutation in parallel	Xilinx Spartan 3	20233 slices	5901 Mbit/s	80.7 MHz
Grøstl-384/512	Submission document	P & Q permutation in parallel	Xilinx Virtex 5	5419 slices	15395 Mbit/s	210.5 MHz
MD6	Submission document	Compression function only, 16 parallel steps	Xilinx Virtex-II Pro	5313 slices	1232 Mbit/s	150.3 MHz
MD6	Submission document	Compression function only, 32 parallel steps	Xilinx Virtex-II Pro	7529 slices	1894 Mbit/s	141.6 MHz

2 High-Speed Implementations (ASIC)

Hash Function Name	Reference	Implementation Details	Technology	Size	Throughput	Clock Frequency
Grøstl-224/256	Submission document	P & Q permutation in parallel	UMC 0.18 µm	131 kGates	4379 Mbit/s	85.5 MHz
Grøstl-384/512	Submission document	P & Q permutation in parallel	UMC 0.18 µm	341 kGates	6225 Mbit/s	85.1 MHz
Keccak	Submission document	Core (round function, state register) & IO buffer	ST 0.13 µm	48 kGates	28400 Mbit/s	500 MHz
Keccak	Submission document	Core (round function, state register) only	ST 0.13 µm	40 kGates	15000 Mbit/s	500 MHz
MD6	Submission document	Compression function only, 48 parallel steps	GPDSK 90 nm	145 kGates	N/A	200 MHz
MD6	Submission document	Compression function & memory control logic, 16 parallel steps	GPDSK 90 nm	105 kGates	N/A	200 MHz

3 Low-Area Implementations (ASIC)

Hash Function Name	Reference	Implementation Details	Technology	Size	Throughput	Clock Frequency
Keccak	Submission document	Core using system memory	ST 0.13 µm	6 kGates	26 Mbit/s(*)	100 MHz

(*) Estimation for 64-bit memory interface based on published performance figures.